1. Field of the Invention
The present invention relates to a flash memory having a spare sector, and more particularly to a flash memory that prevents access time delays owing to determination of whether or not there has been replacement to the spare sector.
2. Description of the Related Art
Flash memory is widely used as a type of non-volatile semiconductor memory. Flash memory is a semiconductor memory comprising a cell transistor having a floating gate or trap gate, and the memory core generally comprises a plurality of sectors. Within each sector a plurality of word lines, a plurality of bit lines, and a plurality of cell transistors are provided, making up the erase units. Consequently, a sector is a kind of memory block, each one having at least a word decoder. In addition to a row address that selects the word line and a column address that selects the bit line, an externally supplied address includes a sector address that selects the sector.
For reasons related to the manufacturing process, it is not easy to eradicate defective bits from semiconductor memory completely. In order to improve the yield rate, therefore, spare memory is installed in advance and if any defective bits are detected during the performance test that is carried out during the last stage of the manufacturing process, then the domain containing the defective bits is replaced by the spare memory. The fact that these bad bits have been replaced by spare memory is recorded in a memory called a redundant memory. Arrangements of this kind using redundant memory have been widely employed in DRAM memory for some time, and have recently come to be employed in flash memory too as the capacity of these devices has increased.
The redundancy structure as employed in DRAM has a spare memory cell array provided in a vertical column direction as well as a regular memory cell array. When a word line is selected in accordance with the row address and driven, a word line common to the regular memory cell array and the spare memory cell array is booted. Parallel with this, a check is carried out to detect whether the external column address corresponds to bad bits that have been replaced, and based on the results of this either the regular memory cell array or the spare memory cell array is selected. An example of a DRAM redundancy structure of this type is described in Japanese Patent Application Laid-open No. 2000-149587.
According to the invention described in Japanese Patent Application Laid-open No. 2000-149587, a column redundancy detection circuit is provided that determines whether the column address supplied matches a bad column and in response to the result of this deactivates the regular column decoder and activates the redundancy column decoder. As a consequence of this the timing set by the regular column selection and the timing set by the redundancy column selection become out of step with one another; one issue arising from this is that it becomes necessary to provide sufficient time between the end of the data line pre-charge and the start of amplification. According to Japanese Patent Application Laid-open No. 2000-149587, a dummy redundancy detection circuit is provided in order to resolve this problem, which detects the unequal redundancy result timing and activates the column decoder on the regular memory cell side and the redundancy column decoder on the spare memory cell side at the same time according to this timing. In this way, it is possible to bring the timing of the column selection on the regular memory cell side and the spare memory cell side into accordance with one another, thus shortening the time mentioned above between the end of the data line pre-charge and the start of amplification.
The flash memory according to the present invention, on the other hand, has a sector structure, with a word decoder provided in each sector. In addition to the regular sectors, a spare sector is provided for rescuing any bad sector. The basic structure of the present invention is thus fundamentally different from that of Japanese Patent Application Laid-open No. 2000-149587. In a flash memory of the sector structure type, then, with the object of shortening access time, both the regular sector and the spare sector are activated in response to an ATD (address transition detection) signal generated when a change in address is detected during access; in parallel with this a check is carried out to detect any spare sector replacement. When the presence or absence of any replacement has been detected, either the regular sector or the spare sector is deactivated. Consequently, there is no discrepancy between the activation timing of the regular sector and the spare sector, and the issues arising differ from those faced when using Japanese Patent Application Laid-open No. 2000-149587.
One issue with a flash memory of the sector-type structure, however, is that the timing of the readout completion of the redundancy memory that stores the replacement information regarding replacement to the spare memory can sometimes fluctuate owing to the circuit design or uneven manufacture. As a consequence of this fluctuation in the timing of the redundancy memory readout completion, a sufficient margin needs to be allowed for when setting the redundancy detection timing.
FIG. 1 shows the operation procedure of conventional redundancy detection. A regular sector selection signal generating circuit 16 and a spare sector selection signal generating circuit 18 are provided in relation to a regular sector SEC and a spare sector SSEC, and a regular sector selection signal RSEC and a spare sector selection signal SSEC are generated. In response to the rising edge of the ATD signal, the selection signal generating circuits 16, 18 set the selection signals RSEC, SSEC to the activated state (H-level) at the same time. In response to this, the row decoders within the regular sector SEC and the redundancy sector SSEC are activated, and begin their decoding operations. Also, in response to the ATD signal, the redundancy memory 10 is activated and starts its readout operation. The redundancy memory 10 comprises a contents addressable memory (CAM) for example; it stores whether the supplied sector address is a replaced sector or not, and outputs this replacement information COUT (CAM output signal). According to the structure of the redundancy memory 10, if replacement with the spare memory is necessary then this replacement information changes from its initial L-level state to H-level, but maintains its L-level if no replacement is necessary. This means that there is no way to determine the timing of the completion of the readout operation from its output COUT.
For this reason, a timing circuit 12 is provided, which generates a ready signal READY having a pulse width of a determined time dt having a sufficient operation margin from the rising edge of the ATD signal; in response to the timing of the rising edge of the ready signal READY, the redundancy memory output circuit 14 supplies the replacement signals COUT-R, COUT-S to the selection signal generating circuits 16, 18. As shown in the timing chart in FIG. 1, if the memory data of the redundancy memory is at RM=1, then it shows that no replacement is necessary; the output COUT=L, the regular sector selection signal RSEC is maintained at H-level, and the spare sector selection signal SSEC is set to L-level. If the memory data of the redundancy memory is at RM=0, on the other hand, it shows that replacement to the spare memory is necessary, and the output COUT=H; the regular sector selection signal RSEC is set to L-level, and the spare sector selection signal SSEC is maintained at H-level.
However, as shown when the memory data of the redundancy memory was at RM=0, even if the readout operation of the redundancy memory 10 is completed faster than the timing of the ready signal READY, the timing of the determination is controlled by the timing of the ready signal; one issue arising from this is that it is not possible to speed up the de-selection of the selection signal generating circuits 16, 18. This in turn leads to the problem of longer access times within the flash memory.
It is an object of the present invention, therefore, to provide a flash memory having a spare sector with a shortened access time.
A further object of the present invention is to provide a flash memory capable of higher-speed redundancy detection.